Prior art gas panel display control systems are not easily adapted to parallel selective manipulation of an entire line of discharge sites spanning one panel coordinate. Thus, since it is usually necessary to interpose at least one sustaining cycle between successive writing operations (to prevent excessive dissipation of existing polorization conditions of the gas panel), the maximum range of panel write/erase manipulation in such systems is significantly curtailed by comparison to a system having full parallel line write/erase capability. The above-mentioned Kleen, et al U.S. Pat. No. 3,811,124 solves this problem with the prior art by including a field effect transistor latch along with the high voltage driver switching circuit. This enables the rapid preconditioning of a large number of the latching FET elements selectively, one at a time (to set up selective drive switching control conditions for parallel manipulation of a full line of panel sites in one coordinate direction, row or column) during a fraction of the quiescient sustaining period preceeding each write/erase manipulation. The contribution of the Kleen, et al patent includes among other things, the association of a latching circuit with the high voltage driver to permit extremely fast preconditioning of the drivers on the order of nanoseconds, in comparison to the minimum duration of a write/erase cycle on the order of multi-microseconds, permitting the selective preconditioning of latching elements associated with an entire line of gas panel displays sites. This permits the manipulation of any part or the whole of a line of panel discharge sites in each write/erase cycle.
The invention disclosed herein, improves upon the design of a high voltage driver and latching circuit shown in FIG. 3 of the Kleen, et al patent by increasing the switching speed of the latching driver circuit while decreasing both the size of the circuit and its heat dissipation.